Field of the Invention
The present invention relates to a semiconductor device and a test method therefor, and more particularly relates to a semiconductor device including a plurality of data input/output terminals and a test method therefor.
Description of Related Art
Various operation tests are performed at each step in a process of manufacturing a semiconductor device. For example, Japanese Patent Application Laid-open No. H5-74898 discloses that a screening test of a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) is performed in a wafer state and then a final test is performed for a packaged semiconductor memory device. It is desirable that the screening test in a wafer state be executed for many semiconductor memory devices in parallel. However, if all data input/output terminals thereof are connected to a probe card, fewer semiconductor memory devices can be tested in parallel and accordingly a method of performing the test using some of the data input/output terminals is proposed (see Japanese Patent Application Laid-open No. 2001-57100).
In the final test after packaging, the semiconductor memory device needs to be operated in a state closer to that in a normal operation than in the screening test. Therefore, all of the data input/output terminals are connected to a tester to write individual test data to each of the data input/output terminals.
As shipment forms of semiconductor memory devices, there is a form in which semiconductor memory devices are shipped in a wafer state in addition to the form in which the packaged semiconductor memory devices are shipped as described in Japanese Patent Application Laid-open No. H5-74898. Also when the semiconductor memory devices are shipped in a wafer state, the final test mentioned above needs to be performed to ensure product quality.
However, when the final test is performed in a wafer state, probe needles of the probe card need to be applied to all data input/output terminals of the semiconductor memory devices to write individual test data to each of the data input/output terminals. Accordingly, the number of semiconductor memory devices that can be tested at the same time is reduced, which increases a test time. When the screening test described in Japanese Patent Application Laid-open No. 2001-57100 is adapted to the final test in a wafer state, the tester can receive read data not being compressed; however, arbitrary test data cannot be written to each of the data input/output terminals.